The present invention relates to semiconductor devices, and more particularly to a technique that is effectively applicable to a semiconductor device including a static random access memory (SRAM).
In a static random access memory (hereinafter referred to just as an SRAM), a memory cell thereof has a performance characteristic known as a static noise margin. The static noise margin represents the degree of stability in retention with respect to data stored in each memory cell. As the static noise margin is increased, the degree of stability in data retention becomes higher, whereas a write of inverted data over existing data retained in memory cells becomes more burdensome. To solve this problem, it is required to enhance a write margin without sacrificing a static noise margin by reducing a power supply voltage applied to memory cells in a write operation to a level lower than that in a read operation, as proposed in Patent Documents 1 and 2 indicated below.
In the Patent Document 1, there is disclosed a circuit configuration wherein power supply lines to memory cells are coupled to complementary bit lines through use of coupling capacitance elements in order to reduce a power supply voltage applied to memory cells in a write operation to a level lower than that in a read operation. Further, the Patent Document 1 discloses another circuit configuration wherein a power supply line is provided for each complementary bit line, and a power switch of each power supply line is controlled by using a logical AND signal of a complementary bit line select signal and a write signal.
In Patent Document 2 indicated below, there is disclosed a circuit configuration wherein a power supply line is provided for each complementary bit line, and a power switch of each power supply line is controlled by a logical AND signal corresponding to a potential of a pair of complementary bit lines. This configuration is based on the condition that amplification on the complementary bit lines is performed on the power supply voltage side in a read operation while a maximum amplitude of power supply voltages is used in a write operation.